The present disclosure relates generally to the systems and method implemented in computer devices and integrated circuit chips for reducing memory energy consumption, e.g., during memory access (read/write) operations; and, more particularly, to a method and apparatus for monitoring usage of memory chips and ranks from a processor, and to use this feedback to a memory controller device to change memory layout and mapping of physical memory to memory chips, and power off unused memory chips and ranks.
Power consumption of a computer system is crucial. Typical memory system power is a significant component of overall power budget. In prior art computer system designs, this power budget can be up to 50% of the overall system power.
Both power supply and heat removal are the problems and, while the patent literature is replete with descriptions of systems and methods that optimize power processor performance or reduce power consumption of the memory system, e.g., such as being placed in a lower power consumption mode, most of the prior memory system power solutions negatively impact processor performance.
Moreover, while processor devices are increasingly operating faster, processors are no longer the most significant power consumers giving way to memory. Currently memory systems further cannot be cooled adequately and, as processor power becomes reduced now is the case that memory consumes more significant portion of power, increasing the cost of such systems. Programs could be run slower effectively to save power. Thus, if a process becomes hot, techniques such as power throttling are implemented and operations switched to a lower power mode of operation (e.g., modify or reduce voltage and frequency in the core so that processor and program operates at slower speeds—an actively managed approach), are available. Other approaches include eliminating power supply to processor “islands”. Each of the approaches that address excessive power consumption issues in processor devices, are not advantageous or even applicable for memory systems that include memory devices, e.g., chips, outside of the processor. For example, dropping voltage and frequency to operate slower can not be used as a way for reducing power consumption of memory chips without affecting processor performance and reliability.
It would be highly desirable to have a method and apparatus to reduce power consumption of memory system without hurting processor performance.